1. Field of the Invention
The present invention relates to a circuit for applying power to a semiconductor device, and in particular, to a power circuit for a static random access memory (SRAM) cell.
2. Background of the Related Art
A static random access memory cell (SRAM) includes a flip-flop having a pair of cross-coupled inverters. The SRAM logic state is determined by the voltage of output terminals of the inverters, such that one of the output terminals of the inverters is at a "LOW" state when the other output terminal is at a "HIGH" state. Because the SRAM maintains a constant, stable state, no periodical refresh operation is required to constantly retain stored information, in contrast to a dynamic random access memory cell (DRAM).
The SRAM carries out a more stable operation and consumes less power than the DRAM. In addition, the SRAM is the most rapidly operated semiconductor memory device due to the self-restoring function of the flip-flop. However, integration is low because at least six elements are needed for each SRAM. As a result, SRAMs having less than or equal to a 1 megabyte storage capacitor generally employ a poly load resistor cell. The benefits of the poly load resistor cell include simplicity and small size.
FIG. 1 shows a circuit diagram of a related art SRAM chip using a poly load resistor cell. The SRAM chip includes a plurality of memory cells 10 driven by a memory cell driving circuit block 20. A memory cell 10 includes first and second NMOS access transistors TA1, TA2, first and second NMOS drive transistors TD1, TD2, first and second resistors RL1, RL2, first and second nodes n1, n2, a bit line BL and a bit bar line /BL, a word line WL, and an external power supply Vcc.
Gates of the first and second access transistors TA1, TA2 are coupled to the word line WL. A first electrode of the first access transistor TA1 is coupled to the bit line BL, and its second electrode is commonly coupled to the first node n1 with the first resistor RL1, a gate of the second drive transistor TD2 and a first electrode of the first drive transistor TD1. Correspondingly, a first electrode of the second access transistor TA2 is coupled to the bit bar line /BL, and its second electrode is commonly coupled to the second node n2 with the second resistor RL2, the gate of the first drive transistor TD1 and a first electrode of the second drive resistor TD2.
The first and second resistors RL1, RL2 are coupled to the external power supply VCCext. The second electrodes of the first and second drive transistors TD2, TD2 are coupled to an external ground voltage VSSext.
The external power supply voltage VCCext applied to the SRAM is applied to the memory cell 10 and the memory cell driving circuit block 20 at an equal level. The power is supplied to the memory cell 10 via the poly resistors RL1, RL2 having a resistance on the order of 10.sup.12.OMEGA., after passing through relatively small metal wires of non-resistance. Since the SRAM cell 10 is configured in a latch form, the application of power to the memory cell 10 results in the nodes n1, n2 being set at opposite power levels. For example, the first node n1 is set at a "HIGH" level and the second node n2 is set at a "LOW" level when power is provided to one of the nodes n1, n2, thus maintaining a stable state.
When the word line WL is transited to the `ON` state and the bit line BL is precharged (generally, a VCC level, a high-impedance state), the first node nil of the memory cell 10 transits to a "HIGH" level, relative to the "LOW" level of the second node n2. The "LOW" node n2 data is then transmitted to the bit line BL. The voltage level of the "HIGH" node nil is determined according to the ratio of the current of the drive transistors and access transistors.
When the word line WL is transited to the `OFF` state, the first and second nodes n1, n2 maintain a stable value based on the relationship between the resistors RL1, RL2 and the drive transistors TD1, TD2. The first drive transistor TD1 is transited to the `OFF` state, and the resistance at that drive transistor TD1 is greater than the resistance of the first resistor RL1. Accordingly, the second drive transistor TD2 is transited to the `ON` state, and the resistance at that state is less than the resistance of the second resistor RL2. As a result, the standby current flows through the transistor TD2.
To reduce the standby current, the second resistor RL2 resistance must be increased. Correspondingly, the first resistor RL1 resistance must be decreased to retain the memory cell 10 data. However, the second resistor RL2 resistance must be smaller, and the first resistor RL1 resistance must be greater when opposite data is employed.
Thus, standby current cannot be reduced simultaneously with cell data retention. The memory cell 10 resistance must be increased to reduce the standby current, but that increase deteriorates the voltage necessary to maintain a data retention state, which is generally less than 1.5V.
When sufficient power is supplied to retain the data, the resistance of the second drive transistor TD2 increases more sharply than at the normal operational state. Because the manual resistor RL2 maintains a relatively constant value, the voltage level of the "LOW" node n2 increases.
Accordingly, when the voltage of the "LOW" node n2 increases, the `OFF` resistance value of the first drive transistor TD1 decreases, and thus decreases the voltage of the "HIGH" node n1. The decreased voltage of the "HIGH" node n1 causes a feedback effect, increasing the voltage of the "LOW" node n2.
If the resistance value is increased to prevent the above-described phenomenon, the data retention voltage is deteriorated. Thus, it is impossible to simultaneously increase the resistance value and satisfy the data retention voltage.
In the related art SRAM cell, when a process change in standby mode reduces the resistance values of the load resistors, the standby current of the cell increases sharply. When the resistance value of the load resistor increases to reduce the standby current, a width or a thickness thereof must be reduced according to a property of the load resistor, which results in opening of the load resistors and low yield. When the resistance values of the load resistors are significantly high, the current flowing through the load resistors is reduced, thereby deteriorating the data retention voltage property.
According to another example of the related art, the voltage level of the internal node may be retained by using a cell external circuit, including a reference voltage generating block (not shown) generating a reference voltage in regard to an external signal. As a result, the chip size is increased, and a significant amount of power is consumed.
As described above, the related art has various disadvantages. In the related art, the current cannot be reduced during standby mode without deteriorating the voltage for retaining cell data. Maintaining that voltage increases the current in standby mode. Further, larger chips that consume more power are required to compensate for the disadvantages, resulting in reduced efficiency of size and speed.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.